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INTEGRATED CIRCUITS
DATA SHEET
SAA7111 Video Input Processor (VIP)
Product specification Supersedes data of 1996 Oct 30 File under Integrated Circuits, IC22 1998 May 15
Philips Semiconductors
Product specification
Video Input Processor (VIP)
CONTENTS 1 2 3 4 5 6 7 8 8.1 8.2 8.2.1 8.2.2 8.3 8.4 8.5 8.6 8.7 8.8 8.9 8.10 8.11 8.11.1 9 10 11 12 13 13.1 13.2 14 15 15.1 16 16.1 16.2 16.2.1 16.2.2 16.2.3 16.2.4 16.2.5 16.2.6 16.2.7 16.2.8 16.2.9 FEATURES APPLICATIONS GENERAL DESCRIPTION QUICK REFERENCE DATA ORDERING INFORMATION BLOCK DIAGRAM PINNING FUNCTIONAL DESCRIPTION Analog input processing Analog control circuits Clamping Gain control Chrominance processing Luminance processing RGB matrix VPO-bus (digital outputs) Synchronization Clock generation circuit Power-on reset and CE input RTCO output The Line-21 text slicer Suggestions for I2C-bus interface of the display software reading line-21 data GAIN CHARTS LIMITING VALUES CHARACTERISTICS TIMING DIAGRAMS CLOCK SYSTEM Clock generation circuit Power-on control OUTPUT FORMATS APPLICATION INFORMATION Layout hints I2C-BUS DESCRIPTION I2C-bus format I2C-bus detail Subaddress 00 Subaddress 02 Subaddress 03 Subaddress 04 Subaddress 05 Subaddress 06 Subaddress 07 Subaddress 08 Subaddress 09 2 16.2.10 16.2.11 16.2.12 16.2.13 16.2.14 16.2.15 16.2.16 16.2.17 16.2.18 16.2.19 16.2.20 16.2.21 17 17.1 17.2 17.3 18 19 20 20.1 20.2 20.3 20.3.1 20.3.2 20.3.3 20.4 21 22 23
SAA7111
Subaddress 0A Subaddress 0B Subaddress 0C Subaddress 0D Subaddress 0E Subaddress 10 Subaddress 11 Subaddress 12 Subaddress 1A (read-only register) Subaddress 1B (read-only register) Subaddress 1C (read-only register) Subaddress 1F (read-only register) FILTER CURVES Anti-alias filter curve Luminance filter curves Chrominance filter curves I2C START SET-UP PACKAGE OUTLINE SOLDERING Introduction Reflow soldering Wave soldering PLCC QFP Method (PLCC and QFP) Repairing soldered joints DEFINITIONS LIFE SUPPORT APPLICATIONS PURCHASE OF PHILIPS I2C COMPONENTS
1998 May 15
Philips Semiconductors
Product specification
Video Input Processor (VIP)
1 FEATURES
SAA7111
* Four analog inputs, internal analog source selectors, e.g. 4 x CVBS or 2 x Y/C or (1 x Y/C and 2 x CVBS) * Two analog preprocessing channels * Fully programmable static gain for the main channels or automatic gain control for the selected CVBS or Y/C channel * Switchable white peak control * Two built-in analog anti-aliasing filters * Two 8-bit video CMOS analog-to-digital converters (ADCs) * On-chip clock generator * Line-locked system clock frequencies * Digital PLL for H-sync processing and clock generation * Requires only one crystal (24.576 MHz) for all standards * Horizontal and vertical sync detection * Automatic detection of 50/60 Hz field frequency and automatic switching between standards PAL and NTSC * Luminance and chrominance signal processing for PAL BGHI, PAL N, PAL M, NTSC M, NTSC N and NTSC 4.43 * User programmable luminance peaking or aperture correction * Cross-colour reduction for NTSC by chrominance comb filtering * PAL delay line for correcting PAL phase errors * Real time status information output (RTCO) * Brightness Contrast Saturation (BCS) control on-chip * The YUV (CCIR-601) bus supports a data rate of: - 864 x fH = 13.5 MHz for 625 line sources - 858 x fH = 13.5 MHz for 525 line sources. * Data output streams for 16, 12 or 8-bit width with the following formats: - 411 YUV (12-bit) - 422 YUV (16-bit) - 422 YUV [CCIR-656] (8-bit) - 565 RGB (16-bit) with dither - 888 RGB (24-bit) with special application. * 720 active samples per line on the YUV bus * One user programmable general purpose switch on an output pin * Built in line-21 text slicer * Power-on control 1998 May 15 3 * Two switchable outputs for the digitized CVBS or Y/C input signals AD1 (7 to 0) and AD2 (7 to 0) via the I2C-bus * Chip enable function (reset for the clock generator) * Compatible with memory-based features (line-locked clock) * Boundary scan test circuit complies with the IEEE Std. 1149.1 - 1990 (ID-Code = 0 7111 02 B) * I2C-bus controlled (full read-back ability by an external controller). 2 APPLICATIONS
* Desktop video * Multimedia * Digital television * Image processing * Video phone. 3 GENERAL DESCRIPTION
The Video Input Processor (VIP) is a combination of a two-channel analog preprocessing circuit including source selection, anti-aliasing filter and ADC, an automatic clamp and gain control, a Clock Generation Circuit (CGC), a digital multi-standard decoder (PAL BGHI, PAL M, PAL N, NTSC M and NTSC N), a brightness/contrast/saturation control circuit and a colour space matrix (see Fig.1). The CMOS circuit SAA7111, analog front-end and digital video decoder, is a highly integrated circuit for desktop video applications. The decoder is based on the principle of line-locked clock decoding and is able to decode the colour of PAL and NTSC signals into CCIR-601 compatible colour component values. The SAA7111 accepts as analog inputs CVBS or S-video (Y/C) from TV or VTR sources. The circuit is I2C-bus controlled.
Philips Semiconductors
Product specification
Video Input Processor (VIP)
4 QUICK REFERENCE DATA SYMBOL VDDD VDDA Tamb PA+D 5 digital supply voltage analog supply voltage operating ambient temperature analog and digital power PARAMETER MIN. 4.5 4.75 0 0.77 TYP. 5.0 5.0 25 1.0
SAA7111
MAX. 5.5 5.25 70 1.26 V V
UNIT
C W
ORDERING INFORMATION PACKAGE
TYPE NUMBER NAME SAA7111WP SAA7111H QFP64 DESCRIPTION plastic quad flat package; 64 leads (lead length 1.6 mm); body 14 x 14 x 2.7 mm VERSION SOT188-2 SOT393-1 PLCC68 plastic leaded chip carrier; 68 leads
1998 May 15
4
Philips Semiconductors
Product specification
Video Input Processor (VIP)
6 BLOCK DIAGRAM
SAA7111
handbook, full pagewidth
BYPASS AOUT AI11 AI12 23 (14) 21 (12) 19 (10) ANALOG PROCESSING AND ANALOG-TODIGITAL CONVERSION AD2 n.c. VSS 7,8,9 (64) 22 (13) CON Y I C-BUS CONTROL I C-BUS INTERFACE
2 2
C/CVBS
AI21 AI22
17 (8) 15 (6)
CHROMINANCE CIRCUIT AND BRIGHTNESS CONTRAST SATURATION CONTROL
UV Y
YUV-to-RGB CONVERSION AND OUTPUT FORMATTER
45 to 50 53 to 62 (34 to 39) (42 to 51) (52) 63 (31) 42
VPO (0 : 15)
FEI HREF
AD1
(53) 64 (61) 4 (62) 5 (63) 6
n.c.
10,36, 37
ANALOG PROCESSING CONTROL
GPSW IICSA SDA SCL
LUMINANCE CIRCUIT Y/CVBS
Y VSSA1-2 VDDA1-2 18,14 (9,5) 20,16 (11,7)
SAA7111
CLOCKS
TDI TCK TMS TRST TDO
12 (3) 2 (59) 13 (4) 1 (58) 11 (2)
TEST CONTROL BLOCK FOR BOUNDARY SCAN TEST AND SCAN TEST (56,40,32,26,19) 67,51,43,35,28
(54) 65 CLOCK GENERATION CIRCUIT POWER-ON CONTROL (55) 66 (21) 30 (22) 31 LFCO (20) 29 (23) 32
XTAL XTALI LLC2 CREF LLC RES
SYNCHRONIZATION CIRCUIT
(57,41,33,25,18) 68,52,44,34,27 VDD1-5
(30) 41 VS HS
(27) 38
(17) 26
(29) 40
(28) 39
(60) 3
(15) 24
(16) 25
(24) 33
MGC653
VSS1-5
VREF RTS0 RTS1 RTCO
VDDA0 VSSA0
CE
The pin numbers given in parenthesis refer to the 64-pin package.
Fig.1 Block diagram.
1998 May 15
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Philips Semiconductors
Product specification
Video Input Processor (VIP)
7 PINNING PINS SYMBOL PLCC68 TRST TCK RTCO IICSA SDA SCL n.c. n.c. n.c. n.c. TDO TDI TMS VSSA2 AI22 VDDA2 AI21 VSSA1 AI12 VDDA1 AI11 VSSS AOUT VDDA0 VSSA0 VREF 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 QFP64 58 59 60 61 62 63 64 - - 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 I I O I I/O I/O - - - - O I I GND I P I GND I P I GND O P GND O I/O DESCRIPTION
SAA7111
Test reset input not (active LOW), for boundary scan test; notes 1, 2, 3 and 4. Test clock input for boundary scan test; note 3. Real time control output: contains information about actual system clock frequency, subcarrier frequency and phase and PAL sequence. I2C-bus slave address select input; 0 48H for write, 49H for read, 1 4AH for write, 4BH for read. I2C-bus serial data input/output. I2C-bus serial clock input/output. Not connected. Not connected. Not connected. Not connected. Test data output for boundary scan test; note 3. Test data input for boundary scan test; note 3. Test mode select input for boundary scan test or scan test; note 3. Ground for analog supply voltage channel 2. Analog input 22. Positive supply voltage (+5 V) for analog channel 2. Analog input 21. Ground for analog supply voltage channel 1. Analog input 12. Positive supply voltage (+5 V) for analog channel 1. Analog input 11. Substrate (connected to analog ground). Analog test output; for testing the analog input channels. Positive supply voltage (+5 V) for internal CGC. Ground for internal CGC. Vertical reference output signal (I2C-bit COMPO = 0) or inverse composite blank signal (I2C-bit COMPO = 1) (enabled via I2C-bit OEHV). Positive digital supply voltage 5 (+5 V). Digital ground for positive supply voltage 5. Line-locked system clock output (27 MHz). Line-locked clock 12 output (13.5 MHz). Clock reference output: this is a clock qualifier signal distributed by the CGC for a data rate of LLC2. Using CREF all interfaces on the VPO-bus are able to generate a bus timing with identical phase. If CCIR-656 format is selected (OFTS0 = 1 and OFTS1 = 1) an inverse composite blank signal (pixel qualifier) is provided on this pin.
VDD5 VSS5 LLC LLC2 CREF
27 28 29 30 31
18 19 20 21 22
P GND O O O
1998 May 15
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Philips Semiconductors
Product specification
Video Input Processor (VIP)
SAA7111
PINS SYMBOL PLCC68 RES 32 QFP64 23 O Reset output (active LOW); sets the device into a defined state. All data outputs are in high impedance state. The I2C-bus is reset (waiting for start condition) note 4. Chip enable; connection to ground forces a reset. Positive digital supply voltage 4 (+5 V). Digital ground for positive supply voltage 4. Not connected. Not connected. Horizontal sync output signal (programmable); the positions of the positive and negative slopes are programmable in 8 LLC increments over a complete line (equals 64 s) via I2C-bus bytes HSB and HSS. Fine position adjustment in 2 LLC increments can be performed via I2C-bits HDEL1 and HDEL0. Two functions output; controlled by I2C-bit RTSE1. RTSE1 = 0: PAL line identifier (LOW = PAL line); indicates the inverted and non-inverted R - Y component for PAL signals. RTSE1 = 1: H-PLL locked indicator; a high state indicates that the internal horizontal PLL has locked. Two functions output; controlled by I2C-bit RTSE0. RTSE0 = 0: odd/even field identification (HIGH = odd field). RTSE0 = 1: vertical locked indicator; a HIGH state indicates that the internal VNL has locked. Vertical sync output signal (enabled via I2C-bit OEHV); this signal indicates the vertical sync with respect to the YUV output. The HIGH period of this signal is approximately six lines if the vertical noise limiter (VNL) function is active. The positive slope contains the phase information for a deflection controller. Horizontal reference output signal (enabled via I2C-bit OEHV); this signal is used to indicate data on the digital YUV bus. The positive slope marks the beginning of a new active line. The HIGH period of HREF is 720 Y samples long. HREF can be used to synchronize data multiplexer/demultiplexers. HREF is also present during the vertical blanking interval. Digital ground for positive supply voltage 3. Positive digital supply voltage 3 (+5 V). Digital VPO-bus (Video Port Out) output signal; higher bits of the 16-bit YUV-bus or the 16-bit RGB-bus output signal. The output data rate, the format and multiplexing scheme of the VPO-bus are controlled via I2C-bits OFTS0 and OFTS1. With I2C-bit VIPB = 1 the six MSBs of the digitized input signal (AD1 [7 to 2]) are connected to these outputs. Digital ground for positive supply voltage 2. Positive digital supply voltage 2 (+5 V). I/O DESCRIPTION
CE VDD4 VSS4 n.c. n.c. HS
33 34 35 36 37 38
24 25 26 - - 27
I P GND - - O
RTS1
39
28
O
RTS0
40
29
O
VS
41
30
O
HREF
42
31
O
VSS3 VDD3 VPO (15 to 10)
43 44 45 to 50
32 33 34 to 39
GND P O
VSS2 VDD2
51 52
40 41
GND P
1998 May 15
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Philips Semiconductors
Product specification
Video Input Processor (VIP)
SAA7111
PINS SYMBOL PLCC68 VPO (9 to 0) 53 to 62 QFP64 42 to 51 O Digital VPO-bus output signal; lower bits of the 16-bit YUV-bus or the 16-bit RGB-bus output signal. The output data rate, the format and multiplexing schema of the VPO-bus are controlled via I2C-bits OFTS0 and OFTS1. With I2C-bit VIPB = 1 the digitized input signals (AD1 [1 and 0] and AD2 [7 to 0]) are connected to these outputs. Fast enable input signal (active LOW); this signal is used to control fast switching on the digital YUV-bus. A HIGH at this input forces the IC to set its Y and UV outputs to the high impedance state; note 4. General purpose switch output; the state of this signal is set via I2C-bus control and the levels are TTL compatible. Second output terminal of crystal oscillator; not connected if external clock signal is used. Input terminal for 24.576 MHz crystal oscillator or connection of external oscillator with CMOS compatible square wave clock signal. Digital ground for positive supply voltage 1. Positive digital supply voltage 1 (+5 V). I/O DESCRIPTION
FEI
63
52
I
GPSW XTAL XTALI VSS1 VDD1 Notes
64 65 66 67 68
53 54 55 56 57
O O I GND P
1. For board design without boundary scan implementation (pin compatibility with the SAA7110) connect the TRST pin to ground. 2. This pin provides easy initialization of BST circuit. TRST can be used to force the TAP (Test Access Port) controller to the Test-Logic-Reset state (normal operation) at once. 3. In accordance with the IEEE1149.1 standard the pads TCK, TDI, TMS and TRST are input pads with an internal pull-up transistor and TDO a 3-state output pad. 4. All pin names that carry an `overscore' have been renamed due to Philips pin name conventions. In previous data sheet versions these pins were marked by the suffix `N', e.g. TRST = TRSTN.
1998 May 15
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Philips Semiconductors
Product specification
Video Input Processor (VIP)
SAA7111
64 GPSW
RTCO
66 XTALI
68 V DD1
62 VPO0
handbook, full pagewidth
n.c. 10 TDO 11 TDI 12 TMS 13 VSSA2 14 AI22 15 VDDA2 16 AI21 17 VSSA1 18 AI12 19 VDDA1 20 AI11 21 VSS 22 AOUT 23 VDDA0 24 VSSA0 25 VREF 26
61 VPO1
IICSA
TRST
67 V SS1
65 XTAL
SDA
TCK
SCL
n.c.
n.c.
n.c.
63 FEI
9
8
7
6
5
4
3
2
1
60 VPO3 59 VPO3 58 VPO4 57 VPO5 56 VPO6 55 VPO7 54 VPO8 53 VPO9
SAA7111
52 VDD2 51 V SS2 50 VPO10 49 VPO11 48 VPO12 47 VPO13 46 VPO14 45 VPO15 44 VDD3
VDD5 27
VSS5 28
LLC 29
LLC2 30
CREF 31
RES 32
CE 33
VDD4 34
VSS4 35
n.c. 36
n.c. 37
HS 38
RTS1 39
RTS0 40
VS 41
HREF 42
VSS3 43
MGC636
Fig.2 Pin configuration (PLCC68).
1998 May 15
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Philips Semiconductors
Product specification
Video Input Processor (VIP)
SAA7111
RTCO
XTALI
VPO0
VPO1 50
n.c.
64
63
62
61
60
59
58
57
56
55
54
53
52
51
n.c. TDO TDI TMS VSSA2 AI22 VDDA2 AI21 VSSA1
1 2 3 4 5 6 7 8
49 48 VPO3 47 VPO4 46 VPO5 45 VPO6 44 VPO7 43 VPO8 42 VPO9 41 VDD2 40 VSS2 39 VPO10 38 VPO11 37 VPO12 36 VPO13 35 VPO14 34 VPO15 33 VDD3 VSS3 32
MBH226
SAA7111
9
AI12 10 VDDA1 11 AI11 12 VSS 13 AOUT 14 VDDA0 15 VSSA0 16 VREF 17 VDD5 18 VSS5 19 LLC 20 LLC2 21 CREF 22 RES 23 CE 24 VDD4 25 VSS4 26 HS 27 RTS1 28 RTS0 29 VS 30 HREF 31
Fig.3 Pin configuration (QFP64).
1998 May 15
10
VPO2
VDD1
IICSA
TRST
VSS1
XTAL
handbook, full pagewidth
GPSW
SDA
TCK
SCL
FEI
Philips Semiconductors
Product specification
Video Input Processor (VIP)
8 8.1 FUNCTIONAL DESCRIPTION Analog input processing
SAA7111
control (AGC) as part of the Analog Input Control (AICO). The AGC (automatic gain control for luminance) is used to amplify a CVBS or Y signal to the required signal amplitude, matched to the ADCs input voltage range. The AGC active time is the sync bottom of the video signal.
The SAA7111 offers four analog signal inputs, two analog main channels with clamp circuit, analog amplifier, anti-alias filter and video CMOS ADC (see Fig.6). 8.2 Analog control circuits
The anti-alias filters are adapted to the line-locked clock frequency with help from a filter control. During the vertical blanking, time gain and clamping control are frozen. 8.2.1 CLAMPING
handbook, halfpage
analog input level +4 dB 0 dB (1 V(p-p) 75 ) -6 dB maximum
controlled ADC input level
The clamp control circuit controls the correct clamping of the analog input signals. The coupling capacitor is also used to store and filter the clamping voltage. An internal digital clamp comparator generates the information with respect to clamp-up or clamp-down. The clamping levels for the two ADC channels are fixed for luminance (60) and chrominance (128). Clamping time in normal use is set with the HCL pulse at the back porch of the video signal.
range 10 dB
0 dB
minimum
MGC660
Fig.5 Automatic gain range.
8.3
handbook, halfpage
Chrominance processing
TV line analog line blanking
225
GAIN 60 1
CLAMP
HCL HSY
MGC661
The 8-bit chrominance signal is fed to the multiplication inputs of a quadrature demodulator, where two subcarrier signals from the local oscillator DTO1 are applied (0 and 90 phase relationship to the demodulator axis). The frequency is dependent on the present colour standard. The output signals of the multipliers are low-pass filtered (four programmable characteristics) to achieve the desired bandwidth for the colour difference signals. The colour difference signals are fed to the Brightness/Contrast/Saturation block (BCS), which includes the following five functions; 1. AGC (automatic gain control for chrominance) 2. Chroma amplitude matching [different gain factors for (R-Y) and (B-Y) to achieve CCIR-601 levels Cr and Cb] 3. Chroma saturation control 4. Luminance contrast and brightness 5. Limiting YUV to the values 1 (min.) and 254 (max.) to fulfil CCIR-601 requirements.
Fig.4
Analog line with clamp (HCL) and gain range (HSY).
8.2.2
GAIN CONTROL
Signal (white) peak control limits the gain at signal overshoots. The flow charts (see Figs 10 and 11) show more details of the AGC. The influence of supply voltage variation within the specified range is automatically eliminated by clamp and automatic gain control. The gain control circuit receives (via the I2C-bus) the static gain levels for the two analog amplifiers or controls one of these amplifiers automatically via a built-in automatic gain 1998 May 15 11
Philips Semiconductors
Product specification
Video Input Processor (VIP)
The burst processing block provides the feedback loop of the chroma PLL and contains; Burst gate accumulator Colour identification and killer Comparison nominal/actual burst amplitude Loop filter chroma gain control Loop filter chroma PLL PAL sequence generation Increment generation for DTO1 with divider to generate stable subcarrier for non-standard signals. The chroma comb filter block eliminates crosstalk between the chrominance channels in accordance with the PAL standard requirements. For NTSC colour standards the chroma comb filter can be used to eliminate crosstalk from luminance to chrominance (cross-colour) for vertical structures. The comb filter can be switched off if desired. The resulting signals are fed to the variable Y-delay compensation, RGB matrix, dithering circuit and output interface, which contains the VPO output formatter and the output control logic (see Fig.7). 8.4 Luminance processing 8.5 RGB matrix
SAA7111
Y, Cr and Cb-data are converted after interpolation into RGB data in accordance with CCIR-601 recommendation. The realized matrix equations consider the digital quantization: R = Y + 1.371 Cr G = Y - 0.336 Cb - 0.698 Cr B = Y + 1.732 Cb. After dithering (noise shaping) the RGB data is fed to the output interface within the VPO-bus output formatter. 8.6 VPO-bus (digital outputs)
The 16-bit VPO-bus transfers digital data from the output interfaces to a feature box or a field memory, a digital colour space converter (SAA7192 DCSC), a video enhancement and digital-to-analog processor (SAA7165 VEDA2) or a colour graphics board (Targa-format) as a graphical user interface. The output data formats are controlled via the I2C-bus bits OFTS0, OFTS1 and RGB888. Timing for the data stream formats, 411 YUV (12-bit), 422 YUV (16-bit), 565 RGB (16-bit) and 888 RGB (24-bit) with an LLC2 data rate, is achieved by marking each second positive rising edge of the clock LLC in conjunction with CREF (clock reference) (except RGB 888, see special application in Fig.27). The higher output signals VPO15 to VPO8 in the YUV format perform the digital luminance signal. The lower output signals VPO7 to VPO0 in the YUV format are the bits of the multiplexed colour difference signals (B-Y) and (R-Y). The arrangement of the RGB 565 and RGB 888 data stream bits on the VPO-bus is given in Table 5. The data stream format 422 YUV (the 8 higher output signals VPO15 to VPO8) in LLC data rate fulfils the CCIR-656 standard with its own timing reference code at the start and end of each video data block. A pixel in the format tables is the time required to transfer a full set of samples. In the event of a 4 : 2 : 2 format two luminance samples are transmitted in comparison to one (B-Y) and one (R-Y) sample within a pixel. The time frames are controlled by the HREF signal.
The 8-bit luminance signal, a digital CVBS format or a luminance format (S-VHS, HI8), is fed through a switchable prefilter. High frequency components are emphasized to compensate for loss. The following chrominance trap filter (f0 = 4.43 or 3.58 MHz centre frequency selectable) eliminates most of the colour carrier signal, therefore, it must be bypassed for S-video (S-VHS, HI8) signals. The high frequency components of the luminance signal can be peaked (control for sharpness improvement via I2C-bus) in two band-pass filters with selectable transfer characteristic. This signal is then added to the original (unpeaked) signal. A switchable amplifier achieves common DC amplification, because the DC gains are different in both chrominance trap modes. The improved luminance signal is fed to the BCS control located in the chrominance processing block (see Fig.8).
1998 May 15
12
Philips Semiconductors
Product specification
Video Input Processor (VIP)
Fast enable is achieved by setting input FEI to LOW. The signal is used to control fast switching on the digital VPO-bus. HIGH on this pin forces the YUV outputs to a high-impedance state (see Figs 15 and 17). The digitized analog PAL or NTSC signals AD1 (7 to 0) and AD2 (7 to 0) are connected directly to the VPO-bus via I2C-bit VIPB = 1. AD1 (7 to 0) VPO (15 to 8) and AD2 (7 to 0) VPO (7 to 0) The selection of the analog input channels are controlled via I2C-bus subaddress 02 MODE select. 8.7 Synchronization
SAA7111
It is possible to force a reset by pulling the CE (chip enable) to ground. After the rising edge of CE and sufficient power supply voltage, the outputs LLC, LLC2, CREF, RTCO, RTS0, RTS1, GPSW and SDA return from 3-state to active, while HREF, VREF, HS and VS remain in 3-state and have to be activated via I2C-bus programming (see Table 4). 8.10 RTCO output
The prefiltered luminance signal is fed to the synchronization stage. Its bandwidth is reduced to 1 MHz in a low-pass filter. The sync pulses are sliced and fed to the phase detectors where they are compared with the sub-divided clock frequency. The resulting output signal is applied to the loop filter to accumulate all phase deviations. Internal signals (e.g. HCL and HSY) are generated in accordance with analog front-end requirements. The output signals HS, VS, and PLIN are locked to the timing reference, guaranteed between the input signal and the HREF signal, as further improvements to the circuit may change the total processing delay. It is therefore not recommended to use them for applications which require absolute timing accuracy on the input signals. The loop filter signal drives an oscillator to generate the line frequency control signal LFCO (see Fig.8). 8.8 Clock generation circuit
The real time control and status output signal contains serial information about the actual system clock (increment of the HPLL), subcarrier frequency [increment and phase (via reset) of the FSC-PLL] and PAL sequence bit. The signal can be used for various applications in external circuits, e.g. in a digital encoder to achieve clean encoding (see Fig.16). 8.11 The Line-21 text slicer
The text slicer block detects and acquires Line-21 closed captioning data from a 525-line CVBS signal. Extended data services on Line-21 Field 2 are also supported. If valid data is detected the two data bytes are stored in two I2C-bus registers. A parity check is also performed and the result is stored in the MSB of the corresponding byte. A third I2C-bus register is provided for data valid and data ready flags. The two bits F1VAL and F2VAL indicate that the input signal carries valid Closed Captioning data on the corresponding fields. The data ready bits F1RDY and F2RDY have to be evaluated if asynchronous I2C-bus reading is used. 8.11.1 SUGGESTIONS FOR I2C-BUS INTERFACE OF THE
DISPLAY SOFTWARE READING LINE-21 DATA
The internal CGC generates all clock signals required for the video input processor. The internal signal LFCO is a digital-to-analog converted signal provided by the horizontal PLL. It is the multiple of the line frequency (6.75 MHz = 432 x fh). Internally the LFCO signal is multiplied by a factor of 2 or 4 in the PLL circuit (including phase detector, loop filtering, VCO and frequency divider) to obtain the LLC and LLC2 output clock signals. The rectangular output clocks have a 50% duty factor (see Fig.22). 8.9 Power-on reset and CE input
There are two methods by which the software can acquire the data; 1. Synchronous reading once per frame (or once per field): It can use either the rising edge (Line-21 Field 1) or both edges (Line-21 Field 1 or 2) of the ODD signal (pin RTSO) to initiate an I2C-bus read transfer of the three registers 1A, 1B and 1C 2. Asynchronous reading: It can poll either the F1RDY bit (Line-21 Field 1) or both F1RDY/F2RDY bits (Line-21 Field 1 or 2). After valid data has been read the corresponding F*RDY bit is set to LOW until new data has arrived. The polling frequency has to be slightly higher than the frame or field frequency, respectively.
A missing clock, insufficient digital or analog VDDA0 supply voltages (below 3.5 V) will initiate the reset sequence; all outputs are forced to 3-state. The indicator output RES is LOW for approximately 128 LLC after the internal reset and can be applied to reset other circuits of the digital TV system. 1998 May 15 13
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n.c. VSSA1 VSSA2 AI22 AI21 VDDA1 VDDA2 AI12 AI11 64 9 5 AOSL (1 : 0) 6 8 11 7 10 12 SOURCE SWITCH FUSE (1 : 0) SOURCE SWITCH CLAMP CIRCUIT ANALOG AMPLIFIER DAC9 ANTI-ALIAS FILTER BYPASS SWITCH ADC2 TEST SELECTOR AND BUFFER 14 AOUT CLAMP CIRCUIT ANALOG AMPLIFIER DAC9 ANTI-ALIAS FILTER BYPASS SWITCH ADC1 FUSE (1 : 0)
MGC655
Philips Semiconductors
Video Input Processor (VIP)
handbook, full pagewidth
14
MODE CONTROL CLAMP CONTROL GAIN CONTROL ANTI-ALIAS CONTROL MODE 0 MODE 1 MODE 2 HCL GLIMB HSY GLIMT WIPA SLTCA
VERTICAL BLANKING CONTROL
ANALOG CONTROL
HOLDG GAFIX WPOFF GUDL0-GUDL2 GAI20-GAI28 GAI10-GAI18 HLNRS UPTCV
VBSL
VBLNK SVREF
8
8
VSSS
13
CROSS
MULTIPLEXER
Product specification
LUM
CHR
AD2BYP AD1BYP
SAA7111
The pin numbers given in parenthesis refer to the 64-pin package.
Fig.6 Analog input processing.
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LUM CHR AD2BYP AD1BYP
n.c. 10 (1) TRST TCK TDI TMS TDO 1 (58) 2 (59) 12 (3) 13 (4) 11 (2) TEST CONTROL BLOCK QUADRATURE DEMODULATOR
Philips Semiconductors
Video Input Processor (VIP)
LOW-PASS CHBW0 CHBW1 BRIGHTNESS, CONTRAST, AND SATURATION CONTROL
(52) 63 (42 to 51), 53 to 62 OUTPUT FORMATTER AND (34 to 39), INTERFACE 45 to 50
FEI
VDD1-5
(57,41,33, 25,18) 68,52,44, 34,27 32 (23) POWER-ON CONTROL
SUBCARRIER GENERATION
HUEC
SUBCARRIER INCREMENT GENERATION AND DIVIDER
PHASE DEMOD. AMPLITUDE DETECTOR
Y
RGB MATRIX RGB
interpolation dithering
VPO (9 : 0) VPO (15 : 10) HREF
The pin numbers given in parenthesis refer to the 64-pin package.
Fig.7 Chrominance circuit.
handbook, full pagewidth
15
BURST GATE ACCUMULATOR LOOP FILTER
RES
GAIN CONTROL AND Y-DELAY COMPENSATION UV
DIT CBR
COMB FILTERS
(31) 42
CE CLOCKS (56,40,32,26,19) 67,51,43,35,28
CSTD 1 CSTD 0 INCS
FCTC CODE
BRIG CONT SATN
DCCF
VSS1-5
OFTS0 OFTS1 RGB888 OEYC OEHV FECO VRLN
GPSW RTSE1 RTSE0 VIPB VLOF COLO COMPO
(60) 3
MGC645
RTCO
LUM
Y
Product specification
SAA7111
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LUM
Philips Semiconductors
Video Input Processor (VIP)
Y
LUMINANCE CIRCUIT
PREFILTER CHROMINANCE TRAP VARIABLE BAND-PASS FILTER WEIGHTING AND ADDING STAGE
PREF
BYPS VBLB
BPSS0 BPSS1 PREF
PREFILTER SYNC
MATCHING AMPLIFIER
APER0 APER1 VBLB
CLOCK CIRCUIT
CLOCKS
VBLB LINE-LOCKED CLOCK GENERATOR PHASE DETECTOR COARSE DAC6 HPLL VTRC EXFIL
LINE 21 TEXT SLICER
SYNC SLICER
PHASE DETECTOR FINE
22 20 21
CREF LLC LLC2
handbook, full pagewidth
16
2
BYTE1 BYTE2 STATUS
SYNCHRONIZATION CIRCUIT
VNOI0 VNOI1 VTRC
I C BUS CONTROL
FIDT
AUFD HSB HSS FSEL VTRC
CLOCK GENERATION CIRCUIT
15 16 24
VDDA0 VSSA0 CE
HLCK STTC
VTRC
INCS DISCRETE TIME OSCILLATOR 2 CRYSTAL CLOCK GENERATOR 55 54 XTALI XTAL
GPSW
53
I C-BUS INTERFACE 61 63 62
2
VERTICAL PROCESSOR 30 29 17
COUNTER
LOOP FILTER 2 28
27 HS
MGC654
IICSA SCL SDA
VS RTS0 VREF
RTS1
Product specification
SAA7111
The pin numbers given in parenthesis refer to the 64-pin package.
Fig.8 Luminance and sync processing.
Philips Semiconductors
Product specification
Video Input Processor (VIP)
9 GAIN CHARTS
SAA7111
handbook, halfpage
MGC648
dB 5.5
factor dB = 20 x log 10 gain =
(
768 - i
3.5
bit [8] = 1 i > 256 bit [8] = 0 i < 256
1.5
-0.5 -2.5 -4.5 0 256 gain value (i) 512
factor dB = 20 x log 10 gain =
Fig.9 Amplifier curve.
handbook, full pagewidth
ANALOG INPUT ADC
NO BLANKING ACTIVE
1
VBLK
0
<- CLAMP
GAIN ->
1
HCL
0
1
HSY
1
CLL
0
0
SBOT
1
+ CLAMP
- CLAMP
NO CLAMP
+ GAIN
- GAIN
WIPE = white peak level (254); SBOT = sync bottom level (1); CLL = clamp level [60 Y (128 C)]; HSY = horizontal sync pulse; HCL = horizontal clamp pulse.
Fig.10 Clamp and gain flow.
1998 May 15
17
(
(
(
257 + i 512
7.5
512
0
1
WIPE
0
fast - GAIN
slow + GAIN
MGC647
Philips Semiconductors
Product specification
Video Input Processor (VIP)
SAA7111
handbook, full pagewidth
ANALOG INPUT AMPLIFIER ANTI-ALIAS FILTER ADC 8 LUMA/CHROMA DECODER gain DAC 9
NO ACTION
1
VBLK 1
0 0
HOLDG
1
X 1
0 0
HSY
0 0 1
>254
1 1 0 1 0
<4
<1
>254
X=0 1 >248 0
X=1
+1/F STOP
+1/L
-1/LLC2
+1/LLC2
-1/LLC2
+/- 0
GAIN ACCUMULATOR (18 BITS) ACTUAL GAIN VALUE 9-BIT (AGV) [-6/+6 dB] 1 0
X 1
HSY 1
0 0
Y
AGV
UPDATE GAIN VALUE 9-BIT
FGV
MGC652
X = system variable; Y = AGV - FGVI > GUDL; VBLK = vertical blanking pulse; HSY = horizontal sync pulse; AGV = actual gain value; FGV = frozen gain value.
Fig.11 Gain flow chart.
1998 May 15
18
Philips Semiconductors
Product specification
Video Input Processor (VIP)
10 LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 134). SYMBOL VDDD VDDA Vdiff Tstg Tamb Tamb(bias) VESD Note 1. Human body model: equivalent to discharging a 100 pF capacitor through a 1.5 k resistor. 11 CHARACTERISTICS VDDD = 4.5 to 5.5 V; VDDA = 4.75 to 5.25 V; Tamb = 25 C; unless otherwise specified. SYMBOL Supplies VDDD IDDD PD VDDA IDDA PA PA+D Analog part Iclamp Vi(p-p) |Zi| Ci cs B diff Gdiff fADC DLE ILE 1998 May 15 clamping current input voltage (peak-to-peak value), AC coupling required input impedance input capacitance channel crosstalk fi = 5 MHz at -3 dB VI = 1.25 V DC coupling capacitor = 10 nF; note 1 clamping current off - 0.55 200 - - - - - 11 - - 19 2 1.0 - - -50 - 1.5 - 10 - - - - 16 - - digital supply voltage digital supply current digital power analog supply voltage analog supply current analog power analog and digital power 4.5 100 0.45 4.75 60 0.32 0.77 5.0 130 0.65 5.0 70 0.35 1.0 5.5 160 0.88 5.25 80 0.38 1.26 PARAMETER CONDITIONS MIN. TYP. PARAMETER digital supply voltage analog supply voltage voltage difference between VSSAall and VSSall storage temperature operating ambient temperature operating ambient temperature under bias electrostatic discharge all pins note 1 CONDITIONS MIN. -0.5 -0.5 - -65 0 -10 -2000
SAA7111
MAX. +6.5 +6.5 100 +150 70 +80 +2000 V V
UNIT
mV C C C V
MAX.
UNIT
V mA W V mA W W A V k pF dB
Analog-to-digital converters bandwidth differential phase (amplifier plus anti-alias filter = bypass) differential gain (amplifier plus anti-alias filter = bypass) ADC clock frequency DC differential linearity error DC integral linearity error 15 2 2 - 0.5 1 MHz deg % MHz LSB LSB
Philips Semiconductors
Product specification
Video Input Processor (VIP)
SAA7111
SYMBOL Digital inputs VIL VIH VIL(xtalI) VIH(xtalI) VILn VIHn ILI Ci(I/O) Ci(n)
PARAMETER
CONDITIONS
MIN. -0.5 -
TYP.
MAX.
UNIT
LOW-level input voltage pins SDA and SCL HIGH-level input voltage pins SDA and SCL LOW-level CMOS input voltage pin XTALI HIGH-level CMOS input voltage pin XTALI LOW-level input voltage all other inputs HIGH-level input voltage all other inputs input leakage current input capacitance input capacitance all other inputs inputs and outputs at high-impedance
+1.5 VDDD + 0.5 0.3VDDD - +0.8 VDDD + 0.5 1 8 8
V V V V V V A pF pF
0.7VDDD - - -
0.7VDDD - -0.5 2.0 - - - - - - - -
Digital outputs VOL VOL VOH VOL(clk) VOH(clk) LOW-level output voltage pins SDA and SCL LOW-level output voltage HIGH-level output voltage LOW-level output voltage for clocks HIGH-level output voltage for clocks SDA/SCL at 3 mA sink current note 2 note 2 - 0 2.4 -0.5 2.6 - - - - - 0.4 0.6 VDDD +0.6 VDDD + 0.5 V V V V V
FEI input timing tSU;DAT tHD;DAT CL tOHD;DAT tPD tPDZ input data set-up time input data hold time 13 3 - - - - - - - - ns ns
Data and control output timing output load capacitance output hold time propagation delay propagation delay to 3-state CL = 15 pF CL = 40 pF 15 5 - - 50 - 21 21 pF ns ns ns
1998 May 15
20
Philips Semiconductors
Product specification
Video Input Processor (VIP)
SAA7111
SYMBOL
PARAMETER
CONDITIONS
MIN. - - - - - - -
TYP.
MAX.
UNIT
Clock output timing (LLC and LLC2) CL(LLC) Tcy LLC tr tf tdLLC2 output load capacitance cycle time duty factors for tLLCH/tLLC and tLLC2H/tLLC2 rise time fall time delay time LLC output to LLC2 output LLC LLC2 CL = 40 pF Vi = 0.6 to 2.6 V Vi = 2.6 to 0.6 V Vi = 1.5 V; LLC/LLC2 = 40 pF 15 35 70 40 - - -1 40 39 78 60 5 5 +1 pF ns ns % ns ns ns
Data qualifier output timing (CREF) tOHD;CREF tPD;CREF output hold time propagation delay from positive edge of LLC CL = 15 pF CL = 40 pF 4 - - - - 20 ns ns
Clock input timing (XTALI) XTALI duty factor for tXTALIH/tXTALI nominal line frequency permissible static deviation nominal frequency 40 - - - - - - - 400 - 60 - - 5.7 - - - - - %
Horizontal PLL fHn fH/fHn fSCn 50 Hz field 60 Hz field Subcarrier PLL nominal subcarrier frequency PAL BGHI and NTSC 443 NTSC M PAL M PAL N fSCH/fSCHn lock-in range 4433619 3579545 3575612 3582056 - Hz Hz Hz Hz Hz 15625 15734 - Hz Hz %
1998 May 15
21
Philips Semiconductors
Product specification
Video Input Processor (VIP)
SAA7111
SYMBOL Crystal oscillator fn f/fn f/fn(T)
PARAMETER
CONDITIONS - - -
MIN.
TYP. -
MAX.
UNIT
nominal frequency permissible nominal frequency deviation permissible nominal frequency deviation with temperature
3rd harmonic
24.576 - -
MHz 10-6 10-6
50 20
CRYSTAL SPECIFICATION (X1) TambX1 CL Rs C1 C0 Notes 1. The levels must be measured with load circuits; 1.2 k at 3 V (TTL load); CL = 50 pF. 2. The effects of rise and fall times are included in the calculation of tOHD;DAT, tPD and tPDZ. Timings and levels refer to drawings and conditions illustrated in Figs 12 and 13. Table 1 Processing delay FUNCTION Without amplifier or anti-alias filter With amplifier, without anti-alias filter With amplifier plus anti-alias filter TYPICAL ANALOG DELAY AI22 -> ADCIN (AOUT) (ns) 14 30 72 139 DIGITAL DELAY ADCIN VPO (LLC-CLOCKS) [YDEL(2 to 0) = 000] operating ambient temperature load capacitance series resonance resistor motional capacitance parallel capacitance 0 8 - - - - - 40 1.5 20% 3.5 20% 70 - 80 - - C pF fF pF
1998 May 15
22
Philips Semiconductors
Product specification
Video Input Processor (VIP)
12 TIMING DIAGRAMS
SAA7111
handbook, full pagewidth
tLLC tLLCL CLOCK OUTPUT LLC t t LLCH tPD 2.4 V 0.6 V
MGC658
2.6 V 1.5 V 0.6 V tr
f
tOHD;DAT OUTPUTS VPO, HREF, VREF, VS, HS
An explanation of the output formats is given in Table 5.
Fig.12 Clock/data timing (8-bit CCIR-656 format of the VPO-bus).
handbook, full pagewidth
tLLC tLLCL
tLLC 2.6 V 1.5 V 0.6 V tr t PD 2.4 V 0.6 V
CLOCK OUTPUT LLC tLLCH tPD OUTPUT CREF tOHD;CREF tdLLC2 CLOCK OUTPUT LLC2 tPD tOHD;DAT OUTPUTS VPO, HREF, VREF, VS, HS tOHD;CREF tdLLC2 tf
2.6 V 1.5 V 0.6 V
2.4 V 0.6 V
MGC659
An explanation of the output formats is given in Table 5. The FEI timing of the VPO-bus is illustrated in Figs 15 and 17.
Fig.13 Clock/data timing (12/16-bit CCIR-601 format of the VPO-bus).
1998 May 15
23
Philips Semiconductors
Product specification
Video Input Processor (VIP)
SAA7111
handbook, full pagewidth
tLLC tLLCL
tLLC 2.4 V 1.5 V 0.6 V
CLOCK OUTPUT LLC tf tr
OUTPUT CREF
,,,, ,,,,, ,,,,, ,,,, ,,,,, ,,,,, ,,,, ,,,,, ,,,,,
tLLCH tPD;CREF tOHD;CREF tOHD;CREF tPD;CREF tOHD;CREF R(7 : 3) G(7 : 5)
2.4 V 1.5 V 0.6 V
RGB (8, 8, 8) data VPO15 to VPO8
2.4 V 1.5 V 0.6 V tOHD;DAT G(4 : 2) B(7 : 3)
RGB (8, 8, 8) data VPO7 to VPO0
,,, ,,,
R(2 : 0) G(1 : 0) B(2 : 0)
,, ,,
tPD
,,, ,,,
tOHD;DAT
2.4 V 1.5 V 0.6 V
MBH227
An explanation of the output formats is given in Table 5.
Fig.14 Clock/data timing for RGB888 output format.
handbook, full pagewidth
LLC
CREF
HREF
tSU;DAT t OHD;DAT PDZ
tHD;DAT
FEI t VPO
tPD
MGC656
to 3-state
from 3-state
I2C-bit FECO = 1.
Fig.15 FEI timing diagram (FEI sampling at CREF = HIGH).
1998 May 15
24
Philips Semiconductors
Product specification
Video Input Processor (VIP)
SAA7111
handbook, full pagewidth
transmitted once per line SEQUENCE RESERVED LOW HIGH INCRHPLL 16
15 01 0
RESERVED
DTO RESET(1) RESERVED 50 Hz fields: 235 60 Hz fields: 232
INCRFSCPLL 45
22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
128 BIT NO.: TIME SLOT:
2
31
16 19
63 67 68
MGC649
(1) Set to zero for one transmission, if a phase reset of the fsc - DTO is applied via I2C-bit CDTO. RTCO sequence is generated in LLC/4. The HPLL increment represents the actual LFCO frequency (fLFCO x 4 = fLLC); 16 LSB from 20, upper four bits are fixed to 0100b INCR HPLL x f XTAL f LFCO = -----------------------------------------------word length DTO2 2 Where: fXTAL = 24.576 MHz, word length DTO2 = 20 bits. The fsc increment represents the actual subcarrier frequency (related to the actual clock); 23 LSB from 24, MSB is 0b. INCR FSCPLL x f XTAL INCR HPLL f sc = ------------------------------------------------------ x --------------------------word length DTO1 19 2 2 Where: word length DTO1 = 24 bits.
Fig.16 Real time control output.
handbook, full pagewidth
LLC
CREF
HREF tSU;DAT FEI t PDZ t VPO
MGC657
tHD;DAT
OHD;DAT
tPD
to 3-state
from 3-state
Timing is compatible with SAA7110; I2C-bit FECO = 0.
Fig.17 FEI timing diagram (FEI sampling at CREF = LOW).
1998 May 15
25
Philips Semiconductors
Product specification
Video Input Processor (VIP)
SAA7111
handbook, full pagewidth
LLC
CREF
LLC2
START OF ACTIVE LINE HREF 0 1 2 3 4
Yn
UVn
U0
V0
U2
V2
U4
END OF ACTIVE LINE HREF 715 716 717 718 719
Yn
UVn
V714
U716
V716
U718
V718
MGC646
Fig.18 HREF timing diagram.
1998 May 15
26
Philips Semiconductors
Product specification
Video Input Processor (VIP)
SAA7111
handbook, full pagewidth
0 50 x 2/LLC CVBS burst
139 x 1/LLC processing delay CVBS->VPO(2)
Y - output HREF (50 Hz) 720 x 2/LLC 7 x 2/LLC RTS1 (PLIN)(1)
sync clipped
12 x 2/LLC 144 x 2/LLC 113 x 2/LLC
4/LLC HS
HS (50 Hz) 108 programming range (step size: 8/LLC) HREF (60 Hz) 3 x 2/LLC
0
-107
16 x 2/LLC 720 x 2/LLC HS (60 Hz) HS (60 Hz) programming range (step size: 8/LLC) -106
MGC664
138 x 2/LLC
107
0
(1) PLIN is switched to output RTS1 via I2C-bit RTSE1 = 0. (2) See Table 1.
Fig.19 Horizontal timing diagram.
1998 May 15
27
Philips Semiconductors
Product specification
Video Input Processor (VIP)
SAA7111
handbook, full pagewidth
622 input CVBS HREF VREF VRLN = 1 VREF VRLN = 0
623
624
625
1
2
3
4
5
6
7
8
22
23
503 x 2/LLC VS RTS0 (ODD)(1)
a: 1st field
310 input CVBS HREF
311
312
313
314
315
316
317
318
319
320
335
336
337
VREF VREF
VRLN = 1 VRLN = 0 71 x 2/LLC
VS
RTS0 (ODD)(1) b: 2nd field
MGC662
(1) ODD is switched to output RTS0 via I2C-bit RTSE0 = 0. The luminance peaking and the chrominance trap are bypassed during VREF = 0 if I2C-bit VBLB is set to logic 1. The chrominance delay line (chroma-comb filter for NTSC, phase error correcting for PAL) is disabled during VREF = 0.
Fig.20 Vertical timing diagram for 50 Hz [nominal input signal VNL in normal mode (VNOI = 00b)].
1998 May 15
28
Philips Semiconductors
Product specification
Video Input Processor (VIP)
SAA7111
handbook, full pagewidth
522 (525)
523 (1)
524 (2)
525 (3)
1 (4)
2 (5)
3 (6)
4 (7)
5 (8)
6 (9)
7 (10)
8 (11)
17 (20)
18 (21)
19 (22)
(2)
input CVBS HREF VRLN = 1 VREF VRLN = 0 VREF 493 x 2/LLC VS RTS0 (ODD)(1) a: 1st field
259 (262) input CVBS HREF VRLN = 1 VREF VRLN = 0 VREF
260 (263)
261 (264)
262 (265)
263 (266)
264 (267)
265 (268)
266 (269)
267 (270)
268 (271)
269 (272)
270 (273)
271 (274)
280 (283)
281 (284)
282 (285)
(2)
61 x 2/LLC VS RTS0 (ODD)(1) b: 2nd field
MGC663
(1) ODD is switched to output RTS0 via I2C-bit RTSE0 = 0. (2) Line numbers in parenthesis refer to CCIR line counting. The luminance peaking and the chrominance trap are bypassed during VREF = 0 if I2C-bit VBLB is set to logic 1. The chrominance delay line (chroma-comb filter for NTSC, phase error correcting for PAL) is disabled during VREF = 0.
Fig.21 Vertical timing diagram for 60 Hz [nominal input signal VNL in normal mode (VNOI = 00b)].
1998 May 15
29
Philips Semiconductors
Product specification
Video Input Processor (VIP)
Table 2 OEYC 0 1 0 1 Notes 1. OFTS(1 : 0) = 10 or 01 or 00. 2. OFTS(1 : 0) = 11. 13 CLOCK SYSTEM 13.1 Clock generation circuit Digital output control VPO FEI 0 0 1 1 15 to 0(1) Z active Z Z 15 to 8(2) Z active Z active 7 to 0(2) Z Z Z Z Table 3 Clock frequencies CLOCK XTAL LLC LLC2 LLC4 LLC8
SAA7111
FREQUENCY (MHz) 24.576 27 13.5 6.75 3.375
The internal CGC generates the system clocks LLC, LLC2 and the clock reference signal CREF. The internal generated LFCO (triangular waveform) is multiplied by 2 or 4 via the analog PLL (including phase detector, loop filter, VCO and frequency divider). The rectangular output signals have a 50% duty factor.
handbook, full pagewidth
LFCO
BAND PASS FC = LLC/4
ZERO CROSS DETECTION
PHASE DETECTION
LOOP FILTER
OSCILLATOR
LLC
DIVIDER 1/2
DIVIDER 1/2
LLC2
DELAY
MGC632
CREF
Fig.22 Block diagram of clock generation circuit.
1998 May 15
30
Philips Semiconductors
Product specification
Video Input Processor (VIP)
13.2 Power-on control
SAA7111
Power-on reset is activated at power-on, chip enable, PLL clock generation failure and if the supply voltage falls below 3.5 V. The RES signal can be applied to reset other circuits of the digital picture processing system.
andbook, full pagewidth
POC VDDA ANALOG
POC VDDD DIGITAL
CLOCK PLL LLC POC LOGIC CE POC DELAY RES
CLK0
CE
XTAL
LLCINT
RESINT
LLC
RES some ms 20 to 200 s PLL-delay <1 ms 896 LCC digital delay 128 LCC
MGC633
CE = chip enable input; XTAL = crystal oscillator output; LLCINT = internal system clock; RESINT = internal reset; LLC = line-locked system clock output; RES = reset output (active LOW).
Fig.23 Power-on control circuit.
1998 May 15
31
Philips Semiconductors
Product specification
Video Input Processor (VIP)
Table 4 Power-on control sequence PIN OUTPUT STATUS VPO15 to VPO0, RTCO, RTS0, RTS1, GPSW, HREF, VREF, HS, VS, LLC, LLC2 and CREF are in high-impedance state LLC, LLC2, CREF, RTCO, RTS0, RTS1, GPSW and SDA become active; VPO15 to VPO0, HREF, VREF, HS and VS are held in high-impedance state VPO15 to VPO0, HREF, VREF, HS and VS are held in high-impedance state FUNCTION
SAA7111
INTERNAL POWER-ON CONTROL SEQUENCE Directly after power-on asynchronous reset Synchronous reset sequence
direct switching to high impedance for 20 to 200 ms internal reset sequence
Status after power-on control sequence 14 OUTPUT FORMATS Table 5 Output formats
after power-on (reset sequence) a complete I2C-bus transmission is required
BUS SIGNAL VPO15 VPO14 VPO13 VPO12 VPO11 VPO10 VPO9 VPO8 VPO7 VPO6 VPO5 VPO4 VPO3 VPO2 VPO1 VPO0 Pixel order Y Pixel order UV Data rates I2C-bus control signals Y07 Y06 Y05 Y04 Y03 Y02 Y01 Y00 U07 U06 V07 V06 X X X X 0
411 (12-BIT) Y17 Y16 Y15 Y14 Y13 Y12 Y11 Y10 U05 U04 V05 V04 X X X X 1 Y27 Y26 Y25 Y24 Y23 Y22 Y21 Y20 U03 U02 V03 V02 X X X X 2 Y37 Y36 Y35 Y34 Y33 Y32 Y31 Y30 U01 U00 V01 V00 X X X X 3
422 (16-BIT)(1) Y07 Y06 Y05 Y04 Y03 Y02 Y01 Y00 U07 U06 U05 U04 U03 U02 U01 U00 0 Y17 Y16 Y15 Y14 Y13 Y12 Y11 Y10 V07 V06 V05 V04 V03 V02 V01 V00 1
CCIR-656 (8-BIT)(2) U07 U06 U05 U04 U03 U02 U01 U00 X X X X X X X X 0 Y07 Y06 Y05 Y04 Y03 Y02 Y01 Y00 X X X X X X X X V07 V06 V05 V04 V03 V02 V01 V00 X X X X X X X X 1 Y17 Y16 Y15 Y14 Y13 Y12 Y11 Y10 X X X X X X X X
RGB (16-BIT)(3) RGB (24-BIT)(3) R4 R3 R2 R1 R0 G5 G4 G3 G2 G1 G0 B4 B3 B2 B1 B0 - - LLC2 OFTS0 = 0 OFTS1 = 0 RGB888 = 0 R7 R6 R5 R4 R3 G7 G6 G5 G4 G3 G2 B7 B6 B5 B4 B3 note 4 R7 R6 R5 R4 R3 G7 G6 G5 R2 R1 R0 G1 G0 B2 B1 B0 note 5
0 LLC2 OFTS0 = 0 OFTS1 = 1 RGB888 = X
0 LLC2 OFTS0 = 1 OFTS1 = 0 RGB888 = X
0 LLC OFTS0 = 1 OFTS1 = 1 RGB888 = X
- LLC OFTS0 = 0 OFTS1 = 0 RGB888 = 1
Notes 1. Values in accordance with CCIR-601. 2. Before and after the video data, video timing codes are inserted in accordance with CCIR-656. 3. Values not defined during HREF = LOW. 4. CREF = 0 (see Fig.14). 5. CREF = 1 (see Fig.14). 1998 May 15 32
Philips Semiconductors
Product specification
Video Input Processor (VIP)
SAA7111
handbook, full pagewidth
+255 +235 white
+255 +240 +212
blue 100% blue 75%
+255 +240 +212
red 100% red 75%
+128
LUMINANCE 100%
+128 U-COMPONENT
colourless
+128 V-COMPONENT
colourless
+44 +16 0 black +16 0
yellow 75% yellow 100%
+44 +16 0
cyan 75% cyan 100%
MGC634
a. Y output range.
CCIR Rec. 602 digital levels.
b. U output range (Cb).
c. V output range (Cr).
Equations for modification to the YUV levels via BCS control I2C bytes BRIG, CONT and SATN. Luminance: CONT Y OUT = Int ----------------- x ( Y - 128 ) + BRIG 71 Chrominance: SATN UV OUT = Int ---------------- x ( Cr, Cb - 128 ) + 128 64 It should be noted that the resulting levels are limited to 1 to 254 in accordance with CCIR-601/656 standard.
Fig.24 VPO output signal range with default BCS settings.
handbook, full pagewidth
quartz (3rd harmonic) 24.576 MHz XTAL C= 10 pF XTALI
65 (54)
XTAL
65 (54)
SAA7111
66 (55) XTALI
SAA7111
66 (55)
L = 10 H 20% C= 10 pF C= 1 nF
MGC635
a. With quartz crystal.
b. With external clock.
The pin numbers given in parenthesis refer to the 64-pin package.
Fig.25 Oscillator application.
1998 May 15
33
Philips Semiconductors
Product specification
Video Input Processor (VIP)
15 APPLICATION INFORMATION
SAA7111
handbook, full pagewidth
VDD VDDA C8 100 nF VSSA
C15 C9 100 nF C7 n.c. VDDA0 VDDA1 TRST 100 nF VDDA2 n.c. TMS TDO TDI n.c. TCK BST VSS VDD1 VDD2 VDD3 VDD4 VDD5 100 nF C14 C13 100 nF 100 nF C12 C11 100 nF 100 nF VSS
24 20 16 13 (15) (11) (7) (4) C4 AI22 R4 VSSA 75 C3 AI21 R3 VSSA 75 C2 AI12 R2 VSSA 75 C1 AI11 R1 VSSA 75 VDDD SCL SDA FEI R6 1 k VSS XTAL Q1(24.576 MHz) XTALI L1 10 H C16 1 nF C17 C18 66 (55) 65 (54) R5 1 k 6 (63) 5 (62) 63 (52) 33 (24) 10 nF 21 (12) 10 nF 19 (10) 10 nF 17 (8) 10 nF 15 (6)
1 12 11 2 (3) (2) (59) (58)
68 52 44 34 27 (57) (41) (33) (25) (18) (34) 45 (35) 46 (36) 47 (37) 48 (38) 49 (39) 50 (42) 53 (43) 54 (44) 55 (45) 56 (46) 57 (47) 58 (48) 59 (49) 60
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 VPO(15 : 0)
SAA7111
(50) 61 (51) 62
(31) 42 (17) 26 (27) 38 (30) 41 (60) 3 (28) 39 (29) 40 (53) 64 (14) 23 (20) 29 (21) 30 (22) 31 (23) 32
HREF VREF HS VS RTCO RTS1 RTS0 GPSW AOUT LLC LLC2 CREF RES
(16) (9) 25 18 VSSA1 VSSA0
(5) (13) (56) (40) (32) (26) (19) (61) (64) 8 14 22 67 51 43 35 28 4 7 VSSA2 IICSA VSS1 VSS2 VSS3 VSS4 VSS5 VSS
9 10 36 37
MGC651
10 pF 10 pF VSS
n.c. n.c. n.c.
n.c. n.c.
n.c.
VSSA
VSS
VSS
The pin numbers given in parenthesis refer to the QFP64 package.
Fig.26 Application diagram.
1998 May 15
34
Philips Semiconductors
Product specification
Video Input Processor (VIP)
SAA7111
handbook, full pagewidth
(34) 45 (35) 46 (36) 47 VPO (15 : 8) (37) 48 (38) 49 (39) 50 (42) 53 (43) 54 (44) 55 (45) 56 (46) 57 VPO (7 : 0) (47) 58 (48) 59 (49) 60 (50) 61 (51) 62
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
VPO (15 : 11) 3
R (7 : 3)
VPO (10 : 8) 3 VPO (7 : 5) 3 VSS OEN D7 D6 D5 D4 D2 D1 D0 VSS VSS VPO (4 : 0) 5 HREF VREF HS VS RTCO RTS1 RTS0 GPSW AOUT LLC CREF RES e.g. VDD O7 O6 O5 O4 O2 O1 00 CLK
G (7 : 5) G (4 : 2)
VDD R (2 : 0) 3 8
R (7 : 0)
G (1 : 0) 2 B (2 : 0) 3 8 8
G (7 : 0) B (7 : 0)
D3 74HCT574 O3
SAA7111
(31) 42 (17) 26 (27) 38 (30) 41 (60) 3 (28) 39 (29) 40 (53) 64 (14) 23 (20) 29 (21) 30 (32) 31 (23) 32
B (7 : 3)
e.g. 74F240 LLC2 LLC2N
MGD137
The pin numbers given in parenthesis refer to the QFP64 package. I2C-bus control bits: OFTS(1 : 0) = 00 (subaddress 10h, bits D7 and D6). RGB888 = 1 (subaddress 12h, bit D3).
Fig.27 Application diagram for RGB 24-bit output format.
15.1
Layout hints
Use separate ground planes for analog and digital ground. Connect these planes at one point directly under the device, by using a zero resistor. Use separate supply lines for analog and digital supply. Place the supply decoupling capacitors nearby the supply pins.
Place the coupling (clamp) capacitors close to the analog input pins. Place the termination resistors close to the coupling capacitors. Care should be exercised concerning the hidden layout capacitors around the crystal application. To avoid reflection effects use serial resistors in the clock, sync and data lines.
1998 May 15
35
Philips Semiconductors
Product specification
Video Input Processor (VIP)
16 I2C-BUS DESCRIPTION 16.1 I2C-bus format Write procedure ACK(s) SUBADDRESS ACK(s) DATA (N BYTES)
SAA7111
Table 6 S
SLAVE ADDRESS W
ACK(s)
P
Table 7 S Sr Table 8
Read procedure (combined format) SLAVE ADDRESS W SLAVE ADDRESS R Description of I2C-bus format DESCRIPTION START condition repeated START condition 0100 1000b (IICSA = LOW) or 0100 1010b (IICSA = HIGH) 0100 1001b (IICSA = LOW) or 0100 1011b (IICSA = HIGH) acknowledge generated by the slave acknowledge generated by the master subaddress byte; see Table 9 data byte, see; note 1 and Table 9 STOP condition read/write control bit; X = 0, order to write (the circuit is slave receiver); X = 1, order to read (the circuit is slave transmitter) read = 49H or 4BH; note 2 write = 48H or 4AH IICSA = 0 or 1 ACK(s) ACK(s) SUBADDRESS DATA (N BYTES) ACK(s) ACK(m) P
CODE S Sr Slave address W Slave address R ACK(s) ACK(m) Subaddress Data P X = LSB slave address Slave address
Subaddress
00H chip version 01H reserved 02H to 05H front-end part 06H to 12H decoder part 13H to 19H reserved 1AH to 1CH Line-21 text slicer part 1DH to 1EH reserved 1FH status byte
read and write; note 3 - read and write read and write - read only - read only
Notes 1. If more than one byte DATA is transmitted then the auto-increment of the subaddress is performed. 2. During slave transmitter mode the SCL-LOW period may be extended by pulling SCL to LOW (in accordance with the I2C-bus specification). 3. The I2C-bus subaddress 00 has to be initialized with 0 before being read.
1998 May 15
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Philips Semiconductors
Product specification
Video Input Processor (VIP)
Table 9 I2C-bus receiver/transmitter overview READ SLAVE ADDRESS 49H and 4BH REGISTER FUNCTION Chip version Reserved Analog input control 1 Analog input control 2 Analog input control 3 Analog input control 4 Horizontal sync start Horizontal sync stop Sync control Luminance control Luminance brightness Luminance contrast Chroma saturation Chroma Hue control Chroma control Reserved Format/delay control Output control 1 Output control 2 Reserved Text slicer status Decoded bytes of the text slicer Reserved Status byte Note 1. All unused control bits must be programmed with 0. 16.2 I2C-bus detail SUBADDR. 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12 13-19 1A 1B 1C 1D-1E 1F D7 ID07
(1)
SAA7111
WRITE 48H and 4AH D5 ID05
(1)
IICSA 0 and 1 D3 ID03
(1)
D6 ID06
(1)
D4 ID04
(1)
D2 ID02
(1)
D1 ID01
(1)
D0 ID00
(1)
FUSE1
(1)
FUSE0 HLNRS GAI16 GAI26 HSB6 HSS6 FSEL PREF BRIG6 CONT6 SATN6 HUEC6 CM99
(1)
GUDL2 VBSL GAI15 GAI25 HSB5 HSS5 EXFIL BPSS1 BRIG5 CONT5 SATN5 HUEC5 CSTD1
(1)
GUDL1 WPOFF GAI14 GAI24 HSB4 HSS4
(1)
GUDL0 HOLDG GAI13 GAI23 HSB3 HSS3 VTRC VBLB BRIG3 CONT3 SATN3 HUEC3 DCCF
(1)
MODE2 GAFIX GAI12 GAI22 HSB2 HSS2 HPLL UPTCV BRIG2 CONT2 SATN2 HUEC2 FCTC
(1)
MODE1 GAI28 GAI11 GAI21 HSB1 HSS1 VNOI1 APER1 BRIG1 CONT1 SATN1 HUEC1 CHBW1
(1)
MODE0 GAI18 GAI10 GAI20 HSB0 HSS0 VNOI0 APER0 BRIG0 CONT0 SATN0 HUEC0 CHBW0
(1)
GAI17 GAI27 HSB7 HSS7 AUFD BYPS BRIG7 CONT7 SATN7 HUEC7 CDTO
(1)
BPSS0 BRIG4 CONT4 SATN4 HUEC4 CSTD0
(1)
OFTS1 GPSW RTSE1
(1) (1)
OFTS0
(1)
HDEL1 FECO
(1) (1) (1)
HDEL0 COMPO CBR
(1) (1)
VRLN OEYC RGB888
(1)
YDEL2 OEHV DIT
(1)
YDEL1 VIPB AOSL1
(1)
YDEL0 COLO AOSL0
(1)
RTSE0
(1) (1)
F2VAL BYTE13 BYTE23
(1)
F2RDY BYTE12 BYTE22
(1)
F1VAL BYTE11 BYTE21
(1)
F1RDY BYTE10 BYTE20
(1)
P1 P2
(1)
BYTE16 BYTE15 BYTE14 BYTE26 BYTE25 BYTE24
(1) (1) (1)
STTC
HLCK
FIDT
GLIMT
GLIMB
WIPA
SLTCA
CODE
The I2C-bus receiver slave address is 48H/49H. Subaddresses 0F, 1D, 1E and 13 to 19 are reserved; subaddress 01 is reserved for chip version.
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Philips Semiconductors
Product specification
Video Input Processor (VIP)
16.2.1 SUBADDRESS 00
SAA7111
Table 10 Chip version SA 00, D7 to D0 CONTROL BITS FUNCTION ID07 Chip version in read mode(1) 0 ID06 0 ID05 0 ID04 0 ID03 X ID02 X ID01 X ID00 X
chip version number Note 1. The I2C-bus subaddress 00 has to be initialized with 0 prior to reading it. 16.2.2 SUBADDRESS 02
reserved for chip name
Table 11 Analog control 1 (mode select; see Figs 28 to 35) SA 02, D2 to D0; note 1 CONTROL BITS D2 TO D0 FUNCTION MODE 2 Mode 0: CVBS (automatic gain) Mode 1: CVBS (automatic gain) Mode 2: CVBS (automatic gain) Mode 3: CVBS (automatic gain) Mode 4: Y (automatic gain) + C (gain channel 2 fixed to GAI2 level) Mode 5: Y (automatic gain) + C (gain channel 2 fixed to GAI2 level) Mode 6: Y (automatic gain) + C (gain channel 2 adapted to Y gain) Mode 7: Y (automatic gain) + C (gain channel 2 adapted to Y gain) Note 1. For modes 0 to 3 use BYPS (SA 09, D7) = 0 (chrominance trap active) and for modes 4 to 7 use BYPS = 1 (chrominance trap bypassed). Table 12 Analog control 1 SA 02, D5 to D3 (see Fig.11) CONTROL BITS D5 TO D3 DECIMAL VALUE 0.... ....7 Table 13 Analog control 1 SA 02, D7 and D6 CONTROL BITS D7 AND D6 ANALOG FUNCTION SELECT FUSE FUSE 1 Amplifier plus anti-alias filter bypassed Amplifier active Amplifier plus anti-alias filter active 0 0 1 1 FUSE 0 0 1 0 1 UPDATE HYSTERESIS FOR 9-BIT GAIN GUDL 2 off 7 LSB 0 1 GUDL 1 0 1 GUDL 0 0 1 0 0 0 0 1 1 1 1 MODE 1 0 0 1 1 0 0 1 1 MODE 0 0 1 0 1 0 1 0 1
1998 May 15
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Philips Semiconductors
Product specification
Video Input Processor (VIP)
SAA7111
AI22 handbook, halfpage AI21
AD2
CHROMA
AI22 handbook, halfpage AI21
AD2
CHROMA
AI12 AI11
AD1
LUMA
MGC637
AI12 AI11
AD1
LUMA
MGC638
Fig.28 Mode 0; CVBS (automatic gain).
Fig.29 Mode 1; CVBS (automatic gain).
AI22 handbook, halfpage AI21
AD2
AI22 handbook, halfpage CHROMA AI21
AD2
CHROMA
AI12 AI11
AD1
LUMA
MGC639
AI12 AI11
AD1
LUMA
MGC640
Fig.30 Mode 2; CVBS (automatic gain).
Fig.31 Mode 3; CVBS (automatic gain).
AI22 handbook, halfpage AI21
AD2
AI22 handbook, halfpage CHROMA AI21
AD2
CHROMA
AI12 AI11
AD1
LUMA
MGC641
AI12 AI11
AD1
LUMA
MGC642
Fig.32 Mode 4 Y (automatic gain) + C (gain channel 2 fixed to GAI1 level).
Fig.33 Mode 5 Y (automatic gain) + C (gain channel 2 fixed to GAI1 level).
AI22 handbook, halfpage AI21
AD2
AI22 handbook, halfpage CHROMA AI21
AD2
CHROMA
AI12 AI11
AD1
LUMA
MGC643
AI12 AI11
AD1
LUMA
MGC644
Fig.34 Mode 6 Y (automatic gain) + C (gain channel 2 adapted to Y gain).
Fig.35 Mode 7 Y (automatic gain) + C (gain channel 2 adapted to Y gain).
1998 May 15
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Philips Semiconductors
Product specification
Video Input Processor (VIP)
16.2.3 SUBADDRESS 03
SAA7111
Table 14 Analog control 2 (AICO2) FUNCTION Static gain control channel 1 (GAI18) Sign bit of gain control Static gain control channel 2 (GAI28) Sign bit of gain control Gain control fix (GAFIX) Automatic gain controlled by MODE 1 and MODE 0 Gain control is user programmable via GAI1 + GAI2 Automatic gain control integration (HOLDG) AGC active AGC integration hold (freeze) White peak off (WPOFF) White peak control active White peak off Vertical blanking select (VBSL) Long vertical blanking Short vertical blanking HL not reference select (HLNRS) Normal clamping by HL not Reference select by HL not 16.2.4 SUBADDRESS 04 HLNRS HLNRS 0 1 D6 D6 VBSL VBSL 0 1 D5 D5 WPOFF WPOFF 0 1 D4 D4 HOLDG HOLDG 0 1 D3 D3 GAFIX GAFIX 0 1 D2 D2 GAI28 see Table 16 D1 GAI18 see Table 15 D0 BIT NAME LOGIC LEVEL CONTROL BIT
Table 15 Gain control analog (AIC03); static gain control channel 1 GAI1 SA 04, D7 to D0 DECIMAL VALUE 0.... ....255 256.... ....511 SIGN BIT GAI18 -5.98 0 0 5.98 0 0 1 1 GAI17 0 1 0 1 GAI16 0 1 0 1 CONTROL BITS D7 TO D0 GAI15 0 1 0 1 GAI14 0 1 0 1 GAI13 0 1 0 1 GAI12 0 1 0 1 GAI11 0 1 0 1 GAI10 0 1 0 1
GAIN (dB)
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Philips Semiconductors
Product specification
Video Input Processor (VIP)
16.2.5 SUBADDRESS 05
SAA7111
Table 16 Gain control analog (AIC04); static gain control channel 2 GAI2 SA 05 \DECIMAL VALUE 0.... ....255 256.... ....511 16.2.6 GAIN (dB) -5.98 0 0 5.98 SIGN BIT (SA 03, D1) GAI28 0 0 1 1 GAI27 0 1 0 1 GAI26 0 1 0 1 CONTROL BITS D7 to D0 GAI25 0 1 0 1 GAI24 0 1 0 1 GAI23 0 1 0 1 GAI22 0 1 0 1 GAI21 0 1 0 1 GAI20 0 1 0 1
SUBADDRESS 06
Table 17 Horizontal sync begin SA 06, D7 to D0 DELAY TIME (STEP SIZE = 8/LLC) -128...-108 -107... ...108 (50 Hz) ...107 (60 Hz) 109...127 (50 Hz) 108...127 (60 Hz) 16.2.7 SUBADDRESS 07 1 0 0 0 1 1 CONTROL BITS D7 to D0 HSB7 HSB6 HSB5 0 1 1 HSB4 1 0 0 HSB3 0 1 1 HSB2 1 1 0 HSB1 0 0 1 HSB0 1 0 1
forbidden (outside available central counter range)
forbidden (outside available central counter range)
Table 18 Horizontal sync stop SA 07 DELAY TIME (STEP SIZE = 8/LLC) -128...-108 -107... ...108 (50 Hz) ...107 (60 Hz) 109...127 (50 Hz) 108...127 (60 Hz) 1 0 0 0 1 1 CONTROL BITS D7 to D0 HSS7 HSS6 HSS5 0 1 1 HSS4 1 0 0 HSS3 0 1 1 HSS2 1 1 0 HSS1 0 0 1 HSS0 1 0 1
forbidden (outside available central counter range)
forbidden (outside available central counter range)
1998 May 15
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Philips Semiconductors
Product specification
Video Input Processor (VIP)
16.2.8 SUBADDRESS 08
SAA7111
Table 19 Sync control SA 08, D7 to D5, D3 to D0 FUNCTION Vertical noise reduction (VNOI) Normal mode Searching mode Free running mode Vertical noise reduction bypassed Horizontal PLL (HPLL) PLL closed PLL open, horizontal frequency fixed TV/VTR mode select (VTRC) TV mode (recommended for poor quality TV signals only) VTR mode (recommended as default setting) Extended loop filter (EXFIL) Word width of the loop filter (LF2) amplification = 16-bit Word width of the loop filter (LF2) amplification = 14-bit Field selection (FSEL) 50 Hz and 625 lines 60 Hz and 525 lines Automatic field detection (AUFD) Field state directly controlled via FSEL Automatic field detection AUFD AUFD 0 1 D7 D7 FSEL FSEL 0 1 D6 D6 EXFIL EXFIL 0 1 D5 D5 VTRC VTRC 0 1 D3 D3 HPLL HPLL 0 1 D2 D2 VNOI1 VNOI0 VNOI1 VNOI0 VNOI1 VNOI0 VNOI1 VNOI0 0 0 0 1 1 0 1 1 D1 D0 D1 D0 D1 D0 D1 D0 BIT NAME LOGIC LEVEL CONTROL BIT
1998 May 15
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Philips Semiconductors
Product specification
Video Input Processor (VIP)
16.2.9 SUBADDRESS 09
SAA7111
Table 20 Luminance control FUNCTION Aperture factor (APER) Aperture factor = 0 Aperture factor = 0.25 Aperture factor = 0.5 Aperture factor = 1.0 Update time interval for AGC value (UPTCV) Horizontal update (once per line) Vertical update (once per field) Vertical blanking luminance bypass (VBLB Active luminance processing Luminance bypass during vertical blanking Aperture band-pass (centre frequency) (BPSS) D5 and D4 Centre frequency = 4.1 MHz Centre frequency = 3.8 MHz; note 1 Centre frequency = 2.6 MHz; note 1 Centre frequency = 2.9 MHz; note 1 Prefilter active (PREF) Bypassed Active Chrominance trap bypass (BYPS) Chrominance trap active; default for CVBS mode Chrominance trap bypassed; default for S-Video mode Note 1. Not to be used with bypassed chrominance trap. BYPS BYPS 0 1 D7 D7 PREF PREF 0 1 D6 D6 BPSS1 BPSS0 BPSS1 BPSS0 BPSS1 BPSS0 BPSS1 BPSS0 0 0 0 1 1 0 1 1 D5 D4 D5 D4 D5 D4 D5 D4 VBLB VBLB 0 1 D3 D3 UPTCV UPTCV 0 1 D2 D2 APER1 APER0 APER1 APER0 APER1 APER0 APER1 APER0 0 0 0 1 1 0 1 1 D1 D0 D1 D0 D1 D0 D1 D0 BIT NAME LOGIC LEVEL CONTROL BIT
1998 May 15
43
Philips Semiconductors
Product specification
Video Input Processor (VIP)
16.2.10 SUBADDRESS 0A Table 21 Luminance brightness control BRIG7 to BRIG0 SA 0A CONTROL BITS D7 to D0 OFFSET BRIG7 255 (bright) 128 (CCIR level) 0 (dark) 16.2.11 SUBADDRESS 0B Table 22 Luminance contrast control CONT7 to CONT0 SA 0B CONTROL BITS D7 to D0 GAIN CONT7 1.999 (maximum) 1.109 (CCIR level) 1.0 0 (luminance off) -1 (inverse luminance) -2 (inverse luminance) 16.2.12 SUBADDRESS 0C Table 23 Chrominance saturation control SATN7 to SATN0 SA 0C CONTROL BITS D7 to D0 GAIN SATN7 1.999 (maximum) 1.0 (CCIR level) 0 (colour off) -1 (inverse chroma) -2 (inverse chroma) 16.2.13 SUBADDRESS 0D Table 24 Chrominance hue control HUEC7 to HUEC0 SA 0D CONTROL BITS D7 to D0 HUE PHASE (DEG) HUEC7 +178.6.... ....0.... ....-180 0 0 1 HUEC6 1 0 0 HUEC5 1 0 0 HUEC4 1 0 0 HUEC3 1 0 0 HUEC2 1 0 0 0 0 0 1 1 SATN6 1 1 0 1 0 SATN5 1 0 0 0 0 SATN4 1 0 0 0 0 SATN3 1 0 0 0 0 SATN2 1 0 0 0 0 0 0 0 0 1 1 CONT6 1 1 1 0 1 0 CONT5 1 0 0 0 0 0 CONT4 1 0 0 0 0 0 CONT3 1 0 0 0 0 0 CONT2 1 1 0 0 0 0 1 1 0 BRIG6 1 0 0 BRIG5 1 0 0 BRIG4 1 0 0 BRIG3 1 0 0 BRIG2 1 0 0
SAA7111
BRIG1 1 0 0
BRIG0 1 0 0
CONT1 1 1 0 0 0 0
CONT0 1 1 0 0 0 0
SATN1 1 0 0 0 0
SATN0 1 0 0 0 0
HUEC1 1 0 0
HUEC0 1 0 0
1998 May 15
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Philips Semiconductors
Product specification
Video Input Processor (VIP)
16.2.14 SUBADDRESS 0E Table 25 Chrominance control SA 0E FUNCTION Chroma bandwidth (CHBW0 and CHBW1) Small bandwidth ( 620 kHz) Nominal bandwidth ( 800 kHz) Medium bandwidth ( 920 kHz) Wide bandwidth ( 1000 kHz) Fast colour time constant (FCTC) Nominal time constant Fast time constant Disable chroma comb filter (DCCF) Chroma comb filter on (during VREF = 1) (see Figures 20 and 21) Chroma comb filter off Colour standard (CSTD0 and CSTD1) Colour standard control automatic switching between PAL BGHI and NTSC M Colour standard control automatic switching between NTSC 4.43 (50 Hz) and PAL 4.43 (60 Hz) Colour standard control automatic switching between PAL N and NTSC 4.43 (60 Hz) Colour standard control automatic switching between NTSC N and PAL M Compatibility to SAA7199 (CM99) Default value To be set if SAA7199 (digital encoder) is used for re-encoding in conjunction with RTCO Clear DTO (CDTO) Disabled Every time CDTO is set, the internal subcarrier DTO phase is reset to 0 and the RTCO output generates a logic 0 at time slot 68 (see RTCO description Fig.16). So an identical subcarrier phase can be generated by an external device (e.g. an encoder). CDTO CDTO 0 1 CM99 CM99 0 1 CSTD1 CSTD0 CSTD1 CSTD0 CSTD1 CSTD0 CSTD1 CSTD0 0 0 0 1 1 0 1 1 DCCF DCCF 0 1 FCTC FCTC 0 1 CHBW1 CHBW0 CHBW1 CHBW0 CHBW1 CHBW0 CHBW1 CHBW0 0 0 0 1 1 0 1 1 BIT NAME LOGIC LEVEL
SAA7111
CONTROL BIT
D1 D0 D1 D0 D1 D0 D1 D0
D2 D2
D3 D3
D5 D4 D5 D4 D5 D4 D5 D4
D6 D6
D7 D7
1998 May 15
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Philips Semiconductors
Product specification
Video Input Processor (VIP)
16.2.15 SUBADDRESS 10 Table 26 Format/delay control SA 10 LUMINANCE DELAY COMPENSATION (STEPS IN 2/LLC) -4... ...0... ...3 CONTROL BITS D2 to D0 YDEL2 1 0 0 YDEL1 0 0 1
SAA7111
YDEL0 0 0 1
Table 27 VREF pulse position and length VRLN SA 10 (D3) VREF at 60 HZ 525 LINES(1) VRLN 0 Length Line number Field 1 Field 2 Note 1. The numbers given in parenthesis refer to CCIR line counting. Table 28 Fine position of HS HDEL0 and HDEL1 SA 10 FINE POSITION OF HS WITH A STEP SIZE OF 2/LLC 0 1 2 3 Table 29 Output format selection OFTS0 and OFTS1 SA 10 CONTROL BITS D7 and D6 FORMATS OFTS1 RGB 565, RGB 888 (dependent on control bit RGB888) see Table 31 YUV 422 16 bits YUV 411 12 bits YUV CCIR-656 8 bits 0 0 1 1 OFTS0 0 1 0 1 CONTROL BITS D5 and D4 HDEL1 0 0 1 1 HDEL0 0 1 0 1 first 19 (22) 282 (285) 240 last 258 (261) 521 (524) first 18 (21) 281 (284) 1 242 last 259 (262) 522 (525) first 24 337 0 286 last 309 622 first 23 336 1 288 last 310 623 VREF at 50 HZ 625 LINES
1998 May 15
46
Philips Semiconductors
Product specification
Video Input Processor (VIP)
16.2.16 SUBADDRESS 11 Table 30 Output control 1 SA 11 FUNCTION Colour on (COLO) Automatic colour killer Colour forced on Decoder VIP bypassed (VIPB) DMSD data to YUV output ADC data to YUV output; dependent on mode settings Output enable horizontal/vertical sync (OEHV) HS, HREF, VREF and VS high impedance inputs Outputs HS, HREF, VREF and VS active Output enable YUV data (OEYC) VPO-bus high-impedance inputs Output VPO-bus active Inverse composite blank (COMPO) VREF is vertical reference VREF is inverse composite blank FEI control (FECO) FEI sampling at CREF = LOW (SAA7110 compatible; see Fig.17) FEI sampling at CREF = HIGH General purpose switch (GPSW) Switches directly pin 64 (53) GPSW; note 1 GPSW GPSW Note 1. The pin number given in parenthesis refers to the 64-pin package. 0 1 FECO FECO 0 1 COMPO COMPO 0 1 OEYC OEYC 0 1 OEHV OEHV 0 1 VIPB VIPB 0 1 COLO COLO 0 1 BIT NAME LOGIC LEVEL
SAA7111
CONTROL BIT
D0 D0
D1 D1
D2 D2
D3 D3
D4 D4
D5 D5
D7 D7
1998 May 15
47
Philips Semiconductors
Product specification
Video Input Processor (VIP)
16.2.17 SUBADDRESS 12 Table 31 Output control 2 SA 12 FUNCTION Analog test select (AOSL) AOUT connected to internal test point 1 AOUT connected to input AD1 AOUT connected to input AD2 AOUT connected to internal test point 2 Dithering (noise shaping) control (DIT) Dithering off Dithering on RGB output format selection (RGB888) RGB565 RGB888 Chroma interpolation filter function (CBR) Cubic interpolation (default) Linear interpolation (lower bandwidth) Real time outputs mode select (RTSE0) ODD switched to output pin 40 (29); note 1 VL switched to output pin 40 (29); note 1 Real time outputs mode select (RTSE1) PLIN switched to output pin 39 (28); note 1 HL switched to output pin 39 (28); note 1 Note 1. The pin number given in parenthesis refers to the 64-pin package. RTSE1 RTSE1 0 1 RTSE0 RTSE0 0 1 CBR CBR 0 1 RGB888 RGB888 0 1 DIT DIT 0 1 AOSL1 AOSL0 AOSL1 AOSL0 AOSL1 AOSL0 AOSL1 AOSL0 0 0 0 1 1 0 1 1 BIT NAME LOGIC LEVEL
SAA7111
CONTROL BIT
D1 D0 D1 D0 D1 D0 D1 D0
D2 D2
D3 D3
D4 D4
D6 D6
D7 D7
1998 May 15
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Philips Semiconductors
Product specification
Video Input Processor (VIP)
16.2.18 SUBADDRESS 1A (READ-ONLY REGISTER) Table 32 Line-21 text slicer status SA 1A I2C-BUS STATUS BIT NAME F1RDY F1VAL F2RDY F2VAL FUNCTION new data on field 1 has been acquired (for asynchronous reading); active HIGH Line-21 of field 1 carries valid data; active HIGH new data on field 2 has been acquired (for asynchronous reading); active HIGH Line-21 of field 2 carries valid data; active HIGH
SAA7111
STATUS BIT D0 D1 D2 D3
16.2.19 SUBADDRESS 1B (READ-ONLY REGISTER) Table 33 First decoded data byte of the text slicer SA 1B I2C-BUS TEXT DATA BITS BYTE1 (6 to 0) P1 data bit 6 to 0 of first data byte parity error flag bit; bit goes HIGH when a parity error has occurred FUNCTION DATA BITS D6 to D0 D7
16.2.20 SUBADDRESS 1C (READ-ONLY REGISTER) Table 34 Second decoded data byte of the text slicer SA 1C I2C-BUS TEXT DATA BITS BYTE2 (6 to 0) P2 FUNCTION data bit 6 to 0 of second data byte parity error flag bit; bit goes HIGH when a parity error has occurred DATA BITS D6 to D0 D7
16.2.21 SUBADDRESS 1F (READ-ONLY REGISTER) Table 35 Status byte SA 1F I2C-BUS STATUS BIT NAME CODE SLTCA WIPA GLIMB GLIMT FIDT HLCK STTC FUNCTION colour signal according to selected standard has been detected; active HIGH slow time constant active in WIPA-mode; active HIGH white peak loop is activated; active HIGH gain value for active luminance channel is limited [min (bottom)]; active HIGH gain value for active luminance channel is limited [max (top)]; active HIGH identification bit for detected field frequency; LOW = 50 Hz and HIGH = 60 Hz status bit for locked horizontal frequency; LOW = locked and HIGH = unlocked status bit for horizontal phase loop; LOW = TV time-constant and HIGH = VTR time-constant STATUS BIT D0 D1 D2 D3 D4 D5 D6 D7
1998 May 15
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Philips Semiconductors
Product specification
Video Input Processor (VIP)
17 FILTER CURVES 17.1 Anti-alias filter curve
SAA7111
MGD138
handbook, full pagewidth
6
V (dB)
0 -6 -12 -18 -24 -30 -36 -42
0
2
4
6
8
10
12
f (MHz)
14
Fig.36 Anti-alias filter.
17.2
Luminance filter curves
MGD139
handbook, full pagewidth
18
VY (dB) 6 (1) (2) (4) (3)
-6
(1) (2) (4) (3)
-18
-30
0
2
4
6
fY (MHz)
8
(1) = 43H; (2) = 53H; (3) = 63H; (4) = 73H.
Fig.37 Luminance control SA 09H, 4.43 MHz Trap/CVBS mode, prefilter on and different aperture band-pass centre frequencies.
1998 May 15
50
Philips Semiconductors
Product specification
Video Input Processor (VIP)
SAA7111
MGD140
handbook, full pagewidth
18
VY (dB) 6 (1) (2) (3) (4) -6 (4) (3) (2) (1)
-18
-30
0
2
4
6
fY (MHz)
8
(1) = 40H; (2) = 41H; (3) = 42H; (4) = 43H.
Fig.38 Luminance control SA 09H, 4.43 MHz Trap/CVBS mode, prefilter on and different aperture factors.
MGD141
handbook, full pagewidth
18
VY (dB) 6 (1) (2) (4) (3) -6 (1) (2) (4) (3) -18
-30
0
2
4
6
fY (MHz)
8
(1) = 03H; (2) = 13H; (3) = 23H; (4) = 33H.
Fig.39 Luminance control SA 09H, 4.43 MHz Trap/CVBS mode, prefilter off and different aperture band-pass centre frequencies.
1998 May 15
51
Philips Semiconductors
Product specification
Video Input Processor (VIP)
SAA7111
MGD142
handbook, full pagewidth
18
VY (dB) 6
(1) (2) (3) (4)
-6
-18
-30
0
2
4
6
fY (MHz)
8
(1) = C0H; (2) = C1H; (3) = C2H; (4) = C3H.
Fig.40 Luminance control SA 09H, Y/C mode, prefilter on and different aperture factors.
MGD143
handbook, full pagewidth
18
VY (dB) 6 (1) (2) (3) (4)
-6
-18
-30
0
2
4
6
fY (MHz)
8
(1) = 80H; (2) = 81H; (3) = 82H; (4) = 83H.
Fig.41 Luminance control SA 09H, Y/C mode, prefilter off and different aperture factors.
1998 May 15
52
Philips Semiconductors
Product specification
Video Input Processor (VIP)
SAA7111
MGD144
handbook, full pagewidth
18
VY (dB) 6 (1) (2) (4) (3)
(1) (2) (4) (3)
-6
-18
-30
0
2
4
6
fY (MHz)
8
(1) = 43H; (2) = 53H; (3) = 63H; (4) = 73H.
Fig.42 Luminance control SA 09H, 3.58 MHz Trap/CVBS mode, prefilter on and different aperture band-pass centre frequencies.
MGD145
handbook, full pagewidth
18
VY (dB) 6 (1) (2) (3) (4) -6 (4) (3) (2) (1)
-18
-30
0
2
4
6
fY (MHz)
8
(1) = 40H; (2) = 41H; (3) = 42H; (4) = 43H.
Fig.43 Luminance control SA 09H, 3.58 MHz Trap/CVBS mode, prefilter on and different aperture factors.
1998 May 15
53
Philips Semiconductors
Product specification
Video Input Processor (VIP)
SAA7111
MGD146
handbook, full pagewidth
18
VY (dB) 6 (1) (2) (4) (3)
-6
(1) (2) (4) (3)
-18
-30
0
2
4
6
fY (MHz)
8
(1) = 03H; (2) = 13H; (3) = 23H; (4) = 33H.
Fig.44 Luminance control SA 09H, 3.58 MHz Trap/CVBS mode, prefilter off and different aperture band-pass centre frequencies.
1998 May 15
54
Philips Semiconductors
Product specification
Video Input Processor (VIP)
17.3 Chrominance filter curves
SAA7111
MGD147
handbook, full pagewidth V
6 0
(dB)
-6 -12 -18 -24 -30 -36 -42 -48 -54 (4) (1) (3) (2) (1) (2) (3) (4)
0
0.54
1.08
1.62
2,16
f(MHz)
2.7
Transfer characteristics of the chroma low-pass dependent on CHBW[1:0] settings. (1) CHBW [1 : 0] = 00; (2) CHBW [1 : 0] = 01; (3) CHBW [1 : 0] = 10; (4) CHBW [1 : 0] = 11.
Fig.45 Chrominance filter.
18 I2C-BUS START SET-UP * The given values force the following behaviour of the SAA7111: - The analog input AI11 expects a signal in CVBS format; analog anti-alias filter active - Automatic field detection - YUV 422/16-bit output format enabled - Outputs HS, HREF, VREF and VS active - Contrast, brightness and saturation control in accordance with CCIR standards - Chrominance processing with nominal bandwidth (800 kHz).
1998 May 15
55
Philips Semiconductors
Product specification
Video Input Processor (VIP)
Table 36 I2C-bus start set-up values SUB (HEX) 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12 13 to 19 1A 1B 1C 1D to 1E 1F Notes 1. All X values must be set to LOW. 2. The I2C-bus subaddress 00 has to be initialized with 0 prior to reading. FUNCTION chip version reserved analog input control 1 analog input control 2 analog input control 3 analog input control 4 horizontal sync start horizontal sync stop sync control luminance control luminance brightness luminance contrast chroma hue control chrominance control reserved format/delay control output control 1 output control 2 reserved text slicer status decoded bytes of the text slicer reserved status byte STTC, HLCK, FIDT, GLIMT, GLIMB, WIPA and SLTCA and CODE 0, 0, 0, 0, F2VAL, F2RDY, F1VAL and F1RDY P1 and BYTE1(6 : 0) P2 and BYTE2(6 : 0) 0 0 0 0 0 0 OFTS(1 : 0), HDEL(1 : 0), VRLN and YDEL(2 : 0) GPSW, X, FECO, COMPO, OEYC, OEHV, VIPB and COLO RTSE(1 : 0), X, CBR, RGB888, DIT and AOSL(1 : 0) FUSE(1 : 0), GUDL(2 : 0) and MODE(2 : 0) X, HLNRS, VBSL, WPOFF, HOLDG, GAFIX, GAI2 and GAI18 GAI(17 : 10) GAI(27 : 20) HSB(7 : 0) HSS(7 : 0) NAME(1) 7 ID0(7 : 0); note 2 0 0 1 0 0 0 1 1 6 0 0 1 0 0 0 1 1 0 0 0 1 1 0 0 0 1 0 0 0 VALUES (BIN) 5 0 0 0 1 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 3 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 1 0 0 2 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 1 0 0
SAA7111
(HEX) 1 0 0 0 1 0 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 1 0 1 0 0 1 0 0 0 1 0 START 00 00 C0 33 00 00 EB E0 88 01 80 47 40 00 01 00 40 1C 03 00
AUFD, FSEL, EXFIL, X, VTRC and HPLL 1 and VNOI(1 : 0) BYPS, PREF, BPSS(1 : 0), VBLB, UPTCV and APER(1 : 0) BRIG(7 : 0) CONT(7 : 0) HUEC(7 : 0) 0 1 0 0 0
chrominance saturation SATN(7 : 0)
CDTO, CM99, CSTD(1 : 0), DCCF, FCTC 0 and CHBW(1 : 0) 0 0 0 0 0
read only register
0
0
00
read only register
1998 May 15
56
Philips Semiconductors
Product specification
Video Input Processor (VIP)
19 PACKAGE OUTLINES PLCC68: plastic leaded chip carrier; 68 leads
SAA7111
SOT188-2
eD y 60 61 X 44 43 Z E A
eE
bp b1 wM
68
1
pin 1 index e
E
HE A A4 A1 (A 3)
k
9
27
k1
Lp detail X
10 e D HD
26 ZD B
vM A
vMB 0 5 scale 10 mm
DIMENSIONS (millimetre dimensions are derived from the original inch dimensions) UNIT
mm inches
A
4.57 4.19
A1 min.
0.51
A3
0.25
A4 max.
3.30 0.13
bp
0.53 0.33
b1
0.81 0.66
D (1)
E (1)
e
eD
eE
HD
HE
k
k1 max.
0.51
Lp
1.44 1.02
v
0.18
w
0.18
y
0.10
Z D(1) Z E (1) max. max.
2.16 2.16
24.33 24.33 23.62 23.62 25.27 25.27 1.22 1.27 24.13 24.13 22.61 22.61 25.02 25.02 1.07
45 o
0.180 0.020 0.01 0.165
0.930 0.930 0.995 0.995 0.048 0.057 0.021 0.032 0.958 0.958 0.020 0.05 0.007 0.007 0.004 0.085 0.085 0.890 0.890 0.985 0.985 0.042 0.040 0.013 0.026 0.950 0.950
Note 1. Plastic or metal protrusions of 0.01 inches maximum per side are not included. OUTLINE VERSION SOT188-2 REFERENCES IEC 112E10 JEDEC MO-047AC EIAJ EUROPEAN PROJECTION
ISSUE DATE 92-11-17 95-03-11
1998 May 15
57
Philips Semiconductors
Product specification
Video Input Processor (VIP)
SAA7111
QFP64: plastic quad flat package; 64 leads (lead length 1.6 mm); body 14 x 14 x 2.7 mm
SOT393-1
c
y X
A 48 49 33 32 ZE
e E HE wM pin 1 index 64 1 bp D HD wM ZD B vM B 16 vMA 17 bp Lp L detail X A A2 A1 (A 3)
e
0
5 scale
10 mm
DIMENSIONS (mm are the original dimensions) UNIT mm A max. 3.00 A1 0.25 0.10 A2 2.75 2.55 A3 0.25 bp 0.45 0.30 c 0.23 0.13 D (1) 14.1 13.9 E (1) 14.1 13.9 e 0.8 HD HE L Lp 1.03 0.73 v 0.16 w 0.16 y 0.10 Z D (1) Z E (1) 1.2 0.8 1.2 0.8 7 0o
o
17.45 17.45 1.60 16.95 16.95
Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT393-1 REFERENCES IEC JEDEC MS-022 EIAJ EUROPEAN PROJECTION
ISSUE DATE 96-05-21 97-08-04
1998 May 15
58
Philips Semiconductors
Product specification
Video Input Processor (VIP)
20 SOLDERING 20.1 Introduction 20.3.2 QFP
SAA7111
There is no soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and surface mounted components are mixed on one printed-circuit board. However, wave soldering is not always suitable for surface mounted ICs, or for printed-circuits with high population densities. In these situations reflow soldering is often used. This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our "IC Package Databook" (order code 9398 652 90011). 20.2 Reflow soldering
Wave soldering is not recommended for QFP packages. This is because of the likelihood of solder bridging due to closely-spaced leads and the possibility of incomplete solder penetration in multi-lead devices. CAUTION Wave soldering is NOT applicable for all QFP packages with a pitch (e) equal or less than 0.5 mm. If wave soldering cannot be avoided, for QFP packages with a pitch (e) larger than 0.5 mm, the following conditions must be observed: * A double-wave (a turbulent wave with high upward pressure followed by a smooth laminar wave) soldering technique should be used. * The footprint must be at an angle of 45 to the board direction and must incorporate solder thieves downstream and at the side corners. 20.3.3 METHOD (PLCC AND QFP)
Reflow soldering techniques are suitable for all PLCC and QFP packages. The choice of heating method may be influenced by larger PLCC or QFP packages (44 leads, or more). If infrared or vapour phase heating is used and the large packages are not absolutely dry (less than 0.1% moisture content by weight), vaporization of the small amount of moisture in them can cause cracking of the plastic body. For more information, refer to the Drypack chapter in our "Quality Reference Handbook" (order code 9397 750 00192). Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. Several methods exist for reflowing; for example, infrared/convection heating in a conveyor type oven. Throughput times (preheating, soldering and cooling) vary between 50 and 300 seconds depending on heating method. Typical reflow peak temperatures range from 215 to 250 C. 20.3 20.3.1 Wave soldering PLCC
During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Maximum permissible solder temperature is 260 C, and maximum duration of package immersion in solder is 10 seconds, if cooled to less than 150 C within 6 seconds. Typical dwell time is 4 seconds at 250 C. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. 20.4 Repairing soldered joints
Wave soldering techniques can be used for all PLCC packages if the following conditions are observed: * A double-wave (a turbulent wave with high upward pressure followed by a smooth laminar wave) soldering technique should be used. * The longitudinal axis of the package footprint must be parallel to the solder flow. * The package footprint must incorporate solder thieves at the downstream corners.
Fix the component by first soldering two diagonallyopposite end leads. Use only a low voltage soldering iron (less than 24 V) applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 C. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 C.
1998 May 15
59
Philips Semiconductors
Product specification
Video Input Processor (VIP)
21 DEFINITIONS Data sheet status Objective specification Preliminary specification Product specification Limiting values
SAA7111
This data sheet contains target or goal specifications for product development. This data sheet contains preliminary data; supplementary data may be published later. This data sheet contains final product specifications.
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. 22 LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale. 23 PURCHASE OF PHILIPS I2C COMPONENTS
Purchase of Philips I2C components conveys a license under the Philips' I2C patent to use the components in the I2C system provided the system conforms to the I2C specification defined by Philips. This specification can be ordered using the code 9398 393 40011.
1998 May 15
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Philips Semiconductors
Product specification
Video Input Processor (VIP)
NOTES
SAA7111
1998 May 15
61
Philips Semiconductors
Product specification
Video Input Processor (VIP)
NOTES
SAA7111
1998 May 15
62
Philips Semiconductors
Product specification
Video Input Processor (VIP)
NOTES
SAA7111
1998 May 15
63
Philips Semiconductors - a worldwide company
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For all other countries apply to: Philips Semiconductors, International Marketing & Sales Communications, Building BE-p, P.O. Box 218, 5600 MD EINDHOVEN, The Netherlands, Fax. +31 40 27 24825 (c) Philips Electronics N.V. 1998
SCA60
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
655102/1200/03/pp64
Date of release: 1998 May 15
Document order number:
9397 750 03116

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